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Integrated Circuit Systems, Inc.
ICS9250-13
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
The ICS9250-13 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro or Cyrix. Eight different reference frequency multiplying factors are externally selectable with smooth frequency transitions. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-13 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Features
3.3V outputs: SDRAM, PCI, REF, 48/24MHz 2.5V or 3.3V outputs: CPU 20 ohm CPU clock output impedance 20 ohm PCI clock output impedance Skew from CPU (earlier) to PCI clock - 1 to 4 ns, center 2.6 ns. No external load cap for CL=18pF crystals 250 ps CPU, PCI clock skew 400ps (cycle to cycle) CPU jitter Smooth frequency switch, with selections from 50 to 83.3 MHz CPU. I2C interface for programming 2ms power up clock stable time Clock duty cycle 45-55%. 56 pin 300 mil SSOP package 3.3V operation, 5V tolerant input. 440LX/EX type chipset Motherboard single chip clock solution.
Block Diagram
Recomended Application:
Pin Configuration
Power Groups
VDDREF = REF (0:1), X1, X2 VDDPCI = PCICLK_F, PCICLK(0:5) VDDSDR = SDRAM (0:11), supply for PLL core, VDD48 = 24MHz, 48MHz VDDLIOAPIC = IOAPIC VDDL2CPU = CPUCLK (0:3)
9250-13 Rev A 3/25/99
56-Pin SSOP
* Internal Pull-up Resistor of 120K to VDD on indicated inputs
Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9250-13
Pin Descriptions
PIN NUMBER 1 2 P I N NA M E VDDREF REF0 FS31, 2 TYPE PWR OUT IN PWR IN OUT PWR OUT IN OUT IN OUT OUT IN DESCRIPTION Ref (0:1), XTAL power supply, nominal 3.3V 14.318 MHz reference clock. Frequency select pin. Latched Input Ground Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V Free running PCI clock Frequency select pin. Latched Input PCI clock output. Frequency select pin. Latched Input PCI clock outputs. PCI clock output. (In desktop mode, MODE=1) Halts PCICLK(0:5) clocks at logic 0 level, when input low (In mobile mode, MODE=0) SDRAM clock outputs. Supply for SDRAM (0:15), PLL Core and 24MHz clocks, nominal 3.3V. Data input for I2C serial input. Clock input of I2C input Supply for 48MHz clocks 3.3V nominal 24MHz output clock Pin 15, pin 54 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input. 48MHz output clock Frequency select pin. Latched Input CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low Supply for CPU (0:3), either 2.5V or 3.3V nominal 14.318 MHz reference clock, (in Desktop Mode, MODE=1) This REF output is the STRONGER buffer for ISA BUS loads. Halts CPUCLK (0:3) clocks at logic 0 level, when input low (in Mobile Mode, MODE=0) IOAPIC c l o c k o u t p u t . 1 4 . 3 1 8 M H z P ow e r e d b y V D D L 1 . Supply for IOAPIC, either 2.5 or 3.3V nominal
3,9,16,22,28, 29, 35, GND 41, 47, 53 4 5 6,14 7 8 10, 11, 12, 13 15 17, 18, 20, 21, 26, 27, 30, 31, 36, 37, 39, 40, 42, 43, 45, 46 19, 25, 38, 44 23 24 32 33 X1 X2 VDDPCI PCICLK_F FS11, 2 PCICLK0 FS21, 2 PCICLK(1:4) PCICLK5 PCI_STOP#1
SDRAM (0:15)
OUT
VDDSDR SDATA SCLK VDD48 24MHz MODE1, 2 48MHz FS0
1, 2
PWR IN IN PWR OUT IN OUT IN OUT PWR OUT IN OUT PWR
34 48, 49, 51, 52 50 54
CPUCLK(0:3) VDDLCPU REF1 CPU_STOP#1
55 56
I OA P I C V D D L I OA P I C
Notes: 1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
2
ICS9250-13
Mode Pin - Power Management Input Control
MODE, Pin 25 (Latched Input) 0 1 Pin 46 CPU_STOP# (INPUT) REF1 (OUTPUT) Pin 15 PCI_STOP# (INPUT) PCICLK5 (OUTPUT)
Power Management Functionality
CPU_STOP# PCI_STOP# CPUCLK Outputs Stopped Low Running Running PCICLK (0:5) Running Running Stopped Low PCICLK_F, REF, 24/48MHz and SDRAM Running Running Running Crystal OSC Running Running Running VCO
0 1 1
1 1 0
Running Running Running
CPU 3.3#_2.5V Buffer selector for CPUCLK and IOAPIC drivers.
CPU3.3#_2.5 Input level (Latched Data) 1 0 Buffer Selected for operation at: 2.5V VDD 3.3V VDD
Functionality
VDD1,2,3 = 3.3V5%, VDDL1,2 = 2.5V5% or 3.35%, TA=0 to 70C Crystal (X1, X2) = 14.31818MHz
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHz) 90.00 89.01 88.00 86.99 85.91 85.01 84.00 82.00 81.01 80.00 83.31 68.49 78.00 75.00 71.99 66.82 SDRAM (MHz) 90.00 89.01 88.00 86.99 85.91 85.01 84.00 82.00 81.01 80.00 83.31 68.49 78.00 75.00 71.99 66.82 PCICLK (MHz) 45.00 44.51 44.00 43.50 42.95 42.51 42.00 41.00 40.00 41.65 34.24 34.24 39.00 37.50 35.99 33.41 R E F, I OA P I C (MHz) 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318
3
ICS9250-13
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit. Controler (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK ACK
Dummy Byte Count
ACK Byte Count
ACK
ACK
Byte 0
Byte 0
ACK
ACK
Byte 1
Byte 1
ACK
ACK
Byte 2
Byte 2
ACK
ACK
Byte 3
Byte 3
ACK
ACK
Byte 4
Byte 4
ACK
ACK
Byte 5
Byte 5
ACK
ACK Stop Bit
Stop Bit
Notes:
1. 2. 3. 4. 5.
6.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 4
ICS9250-13
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit Bit 7
Description 0 - 0.25% Spread Spectrum Modulation 1 - 0.6% Spread Spectrum Modulation CPUCLK SDRAM PCICLK Bit (2,6:4) (MHz) (MHz) (MHz)
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 90.00 89.01 88.00 86.99 85.91 85.01 84.00 82.00 81.01 80.00 83.31 68.49 78.00 75.00 71.99 66.82 90.00 89.01 88.00 86.99 85.91 85.01 84.00 82.00 81.01 80.00 83.31 68.49 78.00 75.00 71.99 66.82 45.00 44.51 44.00 43.50 42.95 42.51 42.00 41.00 40.51 40.00 41.65 34.24 39.00 37.50 35.99 33.41
PWD 1
Bit (2,6:4)
XXX Note 1
Bit 3 Bit 1 Bit 0
0-Frequency is selected by hardware select, latched inputs 1- Frequency is selected by Bit 2,6:4 0 - Normal operation 1 - Spread Spectrum Enabled 0 - Running 1 - Tristate all outputs
0 1 0
Note 1. Default at Power-up will be for latched logic inputs to define frequenc,. Bits 2, 6:4 are default to 0000.
5
ICS9250-13
Byte 1: Control Register (1 = enable, 0 = disable)
Byte 2: Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin # 48 49 51 52
PWD Description 1 (Reserved) 1 (Reserved) X FS2# X FS0# 1 CPUCLK3 (Act/Inact) 1 CPUCLK2 (Act/Inact) 1 CPUCLK1 (Act/Inact) 1 CPUCLK0 (Act/Inact)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. Byte 3: Control Register (1 = enable, 0 = disable)
Bit Pin # PWD Description Bit 7 X FS3# Bit 6 7 1 PCICLK_F (Act/Inact) Bit 5 15 1 PCICLK5 (Act/Inact) Bit 4 13 1 PCICLK4 (Act/Inact) Bit 3 12 1 PCICLK3 (Act/Inact) Bit 2 11 1 PCICLK2 (Act/Inact) Bit 1 10 1 PCICLK1 (Act/Inact) Bit 0 8 1 PCICLK0 (Act/Inact) Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Byte 4: Control Register (1 = enable, 0 = disable)
Bit Pin # PWD Description Bit 7 36 1 SDRAM7 (Act/Inact) Bit 6 37 1 SDRAM6 (Act/Inact) Bit 5 39 1 SDRAM5 (Act/Inact) Bit 4 40 1 SDRAM4 (Act/Inact) Bit 3 42 1 SDRAM3 (Act/Inact) Bit 2 43 1 SDRAM2 (Act/Inact) Bit 1 45 1 SDRAM1 (Act/Inact) Bit 0 46 1 SDRAM0 (Act/Inact) Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Byte 5: Control Register (1 = enable, 0 = disable)
Bit Pin # PWD Bit 7 26 1 Bit 6 27 1 Bit 5 30 1 Bit 4 31 1 Bit 3 17 1 Bit 2 18 1 Bit 1 20 1 Bit 0 21 1 Notes: 1. Inactive means outputs are from switching.
Description SDRAM15 (Act/Inact) SDRAM14 (Act/Inact) SDRAM13 (Act/Inact) SDRAM12 (Act/Inact) SDRAM11 (Act/Inact) SDRAM10 (Act/Inact) SDRAM9 (Act/Inact) SDRAM8 (Act/Inact)
held LOW and are disabled
Bit Pin # PWD Description Bit 7 1 (Reserved) Bit 6 1 (Reserved) Bit 5 1 (Reserved) Bit 4 55 1 IOAPIC (Act/Inact) Bit 3 X FS1# Bit 2 1 (Reserved) Bit 1 54 1 REF1 (Act/Inact) Bit 0 2 1 REF0 (Act/Inact) Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
6
ICS9250-13
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9250-13. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes: 1. All timing is referenced to the internal CPU clock. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9250-13. 3. All other clocks continue to run undisturbed. (including SDRAM outputs).
7
ICS9250-13
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9250-13. It is used to turn off the PCICLK (0:5) clocks for low power operation. PCI_STOP# is synchronized by the ICS9250-13 internally. The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9248. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state.
8
ICS9250-13
Shared Pin Operation Input/Output Pins
Pins 2, 7, 8, 25, and 26 on the ICS9250-13 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm(10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figs. 1 and 2 show the recommended means of implementing this function. In Fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the devices internal logic. Figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. These figures illustrate the optimal PCB physical layout options. These configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. The layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s).
Fig. 1
9
ICS9250-13
Fig. 2a
Fig. 2b
10
ICS9250-13
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 7.0 V GND 0.5 V to VDD +0.5 V 0C to +70C 65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V 5% VDDL = 2.5V 5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Input Frequency Input Capacitance1 Transition Time1 Settling Time
1 1
SYMBOL VIH VIL IIH IIL1 IIL2 IDD2.5OP Fi C IN CINX TTrans Ts TSTAB TCPU-PCI2 TCPU-SDRAM2
CONDITIONS
MIN 2 VSS-0.3 -5 -200 12 27
TYP
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66MHz VDD = 3.3 V Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From VDD = 3.3 V to 1% target Freq. VT = 1.5 V VT = 1.5 V
0.1 2.0 -100 14.32 36 1.3 0.3 <2 2.15 70
MAX VDD+0.3 0.8 5
160 16 5 45 2 2 4 500
UNITS V V A A A mA MHz pF pF ms ms ns ps
Clk Stabilization Skew1
1
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP Operating Supply Current IDD2.5OP CL = 0 pF; Select @ 66.8 MHz Skew1
1
MAX 20 4 500
UNITS mA ns ps
TCPU-PCI2 VT=1.5 V; VTL=1.25 V TCPU-SDRAM2 VT=1.5 V;VTL=1.25 V
1
2.15 70
Guaranteed by design, not 100% tested in production.
11
ICS9250-13
Electrical Characteristics - SDRAM
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN IOH = -25 mA 2.4 Output High Voltage VOH3 IOL = 20 mA Output Low Voltage VOL3 VOH = 2.0 V Output High Current IOH3 VOL = 0.8 V 35 Output Low Current IOL3 1 VOL = 0.4 V, VOH = 2.4 V Rise Time Tr3 1 VOH = 2.4 V, VOL = 0.4 V Fall Time Tf3 1 VT = 1.5 V 46 Duty Cycle Dt3 1 Skew Tsk1 VT = 1.5 V
1
TYP 2.85 0.35 -60 45 1.6 1.8 52 325
MAX UNITS V 0.4 V -40 mA mA 2.4 ns 2.2 ns 56 % 500 ps
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN IOH = -8.0 mA 2 Output High Voltage VOH2B IOL = 12 mA Output Low Voltage VOL2B Output High Current IOH2B VOH =1.7 V Output Low Current IOL2B VOL = 0.7 V 19 1 VOL = 0.4 V, VOH = 2.0 V Rise Time tr2B 1 VOH = 2.0 V, VOL = 0.4 V Fall Time tf2B VT = 1.25 V 45 Duty Cycle dt2B1 1 VT = 1.25 V Skew tsk2B 1 Jitter, Cycle-to-cycle tjcyc-cyc2B VT = 1.25 V, Normal or Spread mode VT = 1.25 V Jitter, One Sigma tj12B1 1 VT = 1.25 V tjabs2B -250 Jitter, Absolute
1
TYP 2.4 0.32 -37 26 1.3 1.5 50 78 170 45 120
MAX UNITS V 0.4 V -16 mA mA 1.9 ns 1.9 ns 55 % 175 ps 350 ps 150 ps 250 ps
Guaranteed by design, not 100% tested in production.
12
ICS9250-13
Electrical Characteristics - PCICLK
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN IOH = -28 mA 2.4 Output High Voltage VOH1 Output Low Voltage VOL1 IOL = 9.4 mA Output High Current IOH1 VOH = 2.0 V Output Low Current IOL1 VOL = 0.8 V 41 Rise Time1 Fall Time Skew
1 1 1 1
TYP 3 0.17 -60 45 1.4 1.4
MAX UNITS V 0.4 V -40 mA mA 2 2 55 500 400 150 250 ns ns % ps ps ps ps
tr1 tf1 dt1 tsk1 tjcyc-cyc1a tj11a tjabs1a
1
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V, Normal or Spread mode VT = 1.5 V VT = 1.5 V -250 45
Duty Cycle
50 280 230 75 160
Jitter, Cycle-to-cycle Jitter, One Sigma Jitter, Absolute1
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN IOH = -8.0 mA 2 Output High Voltage VOH4B IOL = 12 mA Output Low Voltage VOL4B VOH =1.7 V Output High Current IOH4B VOL = 0.7 V 19 Output Low Current IOL4B VOL = 0.4 V, VOH = 2.0 V Rise Time tr4B1 VOH = 2.0 V, VOL = 0.4 V Fall Time tf4B1 1 VT = 1.25 V 45 Duty Cycle dt4B VT = 1.25 V Jitter, One Sigma tj14B1 VT = 1.25 V tjabs4B1 -800 Jitter, Absolute
1
TYP 2.3 0.3 -26 27 1.3 1.35 52 235 510
MAX UNITS V 0.4 V -15 mA mA 2.2 ns 2 ns 55 % 350 ps 800 ps
Guaranteed by design, not 100% tested in production.
13
ICS9250-13
Electrical Characteristics - REF, 24 MHz, 48 MHz
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN IOH = -12 mA 2.4 Output High Voltage VOH5 IOL = 10 mA Output Low Voltage VOL5 VOH = 2.0 V Output High Current IOH5 VOL = 0.8 V 16 Output Low Current IOL5 Rise Time1 Fall Time
1 1 1
TYP 2.9 0.3 -30 23 1.95 2.1
MAX UNITS V 0.4 V -20 mA mA 4 4 55 400 800 ns ns % ps ps
tr5 tf5 dt5 tj1s5 tjabs5
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V -800 45
Duty Cycle
51 170 400
Jitter, One Sigma Jitter, Absolute1
1
Guaranteed by design, not 100% tested in production.
14
ICS9250-13
SYMBOL A A1 A2 B C D E e H h L N
X
COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .006 .0085 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0 5 8 .085 .093 .100
VARIATIONS AD MIN. .720
D NOM. .725
N MAX. .730 56
SSOP Package
Ordering Information
ICS9250yF-13
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
15
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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